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System Scaling Committee
What is System Scaling?
New sub-10nm process technologies continue to drive Moore’s Law and promise increased density, lower power and higher performance. At the same time, new markets, such as IoT, are disrupting the market with requirements for high volumes and low cost, but with densities, performance and power requirements that in many cases can be well served by mature process technologies.
System scaling is not new, but it is taking center stage as the market looks for integration alternatives. It offers an excellent alternative path to pursuing Moore’s Law by moving the integration focus from the transistor to the system through the integration of multiple heterogeneous pre-fabricated and proven devices (in the form of die-level IP) into an advanced IC package. In other words, instead of connecting transistors, we are now connecting higher-level blocks (die) directly to each other and gaining the benefits of lower cost, lower power consumption and higher performance.
The new ESD Alliance System Scaling Committee looks to the future by providing the forum to enable cooperation between modeling, design, manufacturing and test to unlock the potential of heterogenous multi-die integration.