Enabling System Scaling

More than Moore - Enabling the Power of System Scaling

The Market is Changing -- Major shifts are rippling through the semiconductor market. New sub-10nm process technologies continue to drive Moore’s Law and promise increased density, lower power and higher performance. Yet, the transition to these advanced nodes are taking longer and the development costs are beyond the economic reach of much of the mainstream market. New markets, such as IoT, are also disrupting the market with requirements for high volumes and low cost, but with densities, performance and power requirements that in many cases can be well served by mature process technologies.

What is System Scaling? -- System scaling is not new, but it is taking center stage as the market looks for integration alternatives. It offers an excellent alternative path to pursuing Moore’s Law by moving the integration focus from the transistor to the system through the integration of multiple heterogeneous pre-fabricated and proven devices (in the form of die-level IP) into an advanced IC package. In other words, instead of connecting transistors, we are now connecting higher-level blocks (die) directly to each other and gaining the benefits of lower cost, lower power consumption and higher performance.

Interposer based IC Design

Too Good to be True? – Good question.  The technologies exist today and some products are already in volume production.  But, is it mainstream?  Not yet -- It will take collaboration and cooperation between modeling, design, analysis/verification, manufacturing and test in order to unlock the potential of these new integration solutions. The ESD Alliance is taking an active role in bringing together the design and manufacturing communities to remove the barriers via an active working comprised of Alliance members from both manufacturing and design.

3D-IC design

Multi-Die IC Design Guide – The ESD Alliance is collaborating with Herb Reiter of eda 2 asic to publish the 2016.6 version of the Multi-Die IC Design guide. The comprehensive guide provides the latest background on multi-die integration techniques and technologies and features information provided by leading vendors that provide solutions and services for multi-die IC design and manufacturing. The guide will be available as a free download from www.esd-alliance.org starting on June 6, 2016. We encourage you to download it and take advantage of the wealth of information provided.

Challenges & Opportunities – The diagram below illustrates the challenges that must be overcome to enable mainstream adoption of system scaling via multi-die ICs. Addressing these challenges requires close cooperation and collaboration between the manufacturing supply chain and the design ecosystem. This in turn will open up new market and revenue opportunities for both suppliers in the design and manufacturing ecosystems.

Manufacturing and Design Automation

System Scaling Working Group – The ESD Alliance represents the collective interests of companies providing goods or services in the semiconductor design ecosystem. Our experience in leading initiatives including export law and regulations, license management systems, anti-piracy, trade show advocacy, market statistics and emerging company support makes us ideally-suited to provide the forum for design and manufacturing companies to discuss collaborative solutions to unlocking the market potential of system scaling via mulit-die IC design and packaging.

JOIN US!  We are actively seeking members to participate in the system scaling working group. Information on membership is available at www.esd-alliance.org or contact us!