ESD Alliance Newsletter - Volume 3, Number 3

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CEO Persective - 20 Years of MSS
Wally Rhines, Chairman & CEO, Mentor Graphics Corporation

[Editor’s note: This edition of the ESD Alliance newsletter introduces a new feature, the CEO Perspective. This will be a series of short articles on various topics by members of the ESD Alliance Board of Directors.]

The year is 1996. EDA revenues for the year totaled $2.3B, which covered a variety of different products and services used by the IC and PCB design communities. The EDA Consortium (as the ESD Alliance was called then) realized a detailed breakdown of that revenue would be a significant source of data for the growing industry. Thus, the Market Statistics Service (MSS) was born. The early MSS reports included industry revenue in CAE, PCB, IC Layout, Semiconductor IP, and Design Services, broken out into 18 detailed product categories and 4 regions.

Fast forward to today, where the most recent report includes 86 product categories, with the most recent 4 quarters revenue totaling $8B. Now as then, the detailed data is provided in complete confidence by public and private industry vendors; aggregated data is then reported each quarter by the ESD Alliance. 

EDA revenue history by categoryThe chart highlights some significant changes in the industry over the last 20 years. In 1996, CAE was by far the most significant category. Semiconductor IP was almost negligible 20 years ago, yet has been the largest single category in recent quarters. In addition to the revenue history by category, the MSS report includes revenue details by region.

Why is this important? Most companies, especially smaller companies, can ill afford to spend valuable resources developing a product for a shrinking market. Should the new sales person be located in the US, Asia, Japan, or Europe? Investors often need quantitative data to support investing in growing the company. What is my share of my specific product markets? Each MSS report includes revenue details for the current year-to-date and the previous 3 years, by quarter, providing valuable data allowing the reader to understand how overall trends and significant quarterly fluctuations can affect their specific business.

Mentor Graphics has contributed data and benefitted from the MSS report since its inception; the data is an important part of our business intelligence.

The MSS report is included along with the many other benefits of membership in the ESD Alliance. For more information about the MSS report, including recent newsletters, visit the MSS Committee page. For more information about the ESD Alliance, visit esd-alliance.org.



ESD Alliance and IEEE CEDA Honor Andrzej Strojwas of CMU with Phil Kaufman Award
Award Ceremony and Dinner to be held January 26th

Andrjez StrojwasThis year’s recipient of the Phil Kaufman Award for Distinguished Contributions to EDA is Andrzej J. Strojwas, Keithley professor of Electrical and Computer Engineering at Carnegie Mellon University.

Presented annually by the ESD Alliance and the IEEE Council on Electronic Design Automation (CEDA), it honors individuals such as Dr. Strojwas who made a demonstrable impact on the field of EDA. He is being recognized for his pioneering research in design for manufacturing. According to Dr. Larry Pileggi, the Tanoto professor of Electrical and Computer Engineering at Carnegie Mellon University, virtually every fab in the world, as well as a vast majority of chips manufactured today, use methodologies he developed. “Since the 1970s, he has done as much as anyone to co-optimize IC design and manufacturing, driving the more sophisticated use of design data in fabs.”

In addition to being the Joseph F. and Nancy Keithley Professor of Electrical and Computer Engineering at Carnegie Mellon University, Dr. Strojwas has served as Chief Technologist at PDF Solutions since 1997. He has held positions at Harris Semiconductor Co., AT&T Bell Laboratories, Texas Instruments, NEC, HITACHI, SEMATECH and KLA-Tencor.

He received multiple awards for the best papers published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Semiconductor Manufacturing and IEEE-ACM Design Automation Conference. Dr. Strojwas is a recipient of the SRC Inventor Recognition Award. He was the Editor of the IEEE Transactions on CAD of ICAS from 1987 to 1989 and served as Technical Program Chairman of the 1988 ICCAD and Conference Chairman of the 1989 ICCAD. In 1990, he was elected IEEE Fellow.

Dr. Strojwas received a Master of Science degree in Electrical Engineering from the Technical University of Warsaw, Poland, and his Ph.D. from Carnegie Mellon University in Pittsburgh.

Since 1994, the Phil Kaufman Award has honored members of our community for their technology innovation, education/mentoring and business or industry leadership. The award was established as a tribute to Phil Kaufman, the late industry pioneer who turned innovative technologies into commercial businesses that have benefited electronic designers. Last year’s recipient was Wally. Rhines, (see his CEO Perspective, above). He was honored for growing the EDA and integrated circuit (IC) design industries through his efforts as a leading voice of EDA and for pioneering the evolution of IC design to SoC design.

We hope you can join us for the award ceremony and dinner to honor Dr. Strojwas. It will be held at the Fourth Street Summit Center in San Jose, Calif., Thursday, January 26th, beginning at 6:30 p.m. To register, go to esd-alliance.org.



Message from the Executive Director
Bob Smith, Executive Director, ESD Alliance

Bob Smith at DVCon EuropeI had the pleasure of attending DVCon Europe in Munich, Germany, last week to give the keynote address at the gala dinner. This was my first visit to the conference and I was impressed. As Oliver Bell of Intel and DVCon’s general chair wrote in his welcome greeting in the program, DVCon Europe is a practical, industry application-oriented conference, focusing on design and verification of electronic systems and integrated circuits. I found that to be absolutely true and then some. According to OneSpin’s Vice President of Marketing Dave Kelf, this year’s promotions chair, the conference attendance increased 20%. Kudos to the Steering Committee.

DVCon Europe is in its third year and, from all I saw, it’s a lively conference full of interesting sessions that ranged from tutorials and panels to keynotes and technical presentations. Twenty-four exhibitors, including ESD Alliance members Cadence, Mentor Graphics, OneSpin Solutions, Sigasi and Synopsys, demonstrating design and verification tools and services rounded out the full two-day event. Of course, conference organizers ensured there was plenty of time for networking and information exchange.

Bob Smith at DVCon EuropeThe dinner was held at the mid-point of conference –– Wednesday evening –– and everyone attending the conference appeared to be there. My talk titled, “Moore’s Law and the Transition from Chip-Centric Design to System-Level Design,” was geared to this European design and verification community. However, the message seems to have international appeal.

It’s apparent that the semiconductor design ecosystem is evolving from a chip-centric focus to a system-centric worldview. While SoCs and other complex semiconductor devices continue to be critical building blocks, the design emphasis is shifting to system design. Moore’s Law remains a key driver, though there are roadblocks and the industry is beginning a transition from integration at the transistor level to integration at the functional or block level.

It’s a great opportunity for many of us in the semiconductor industry and especially attendees at DVCon Europe and similar conferences. And, in fact, it’s why we rebranded the 27-year old EDA Consortium to the ESD Alliance earlier this year to meet the requirements of this evolution. If you haven’t looked lately, please check out the ESD Alliance website to see a refreshed mission acknowledging the breadth of activity we’re undertaken to support the entire system design ecosystem.

Bob Smith at DVCon EuropeI thank the DVCon Steering Committee, especially Oliver Bell and Dave Kelf for inviting me to deliver the keynote and giving me the chance to observe a healthy and vibrant European conference. If you’re planning ahead, the original DVCon will be held in February 27th-March 2nd, 2017 in San Jose, Calif. And, the inaugural DVCon China is slated for April 19th, 2017 in Shanghai, China.

The ESD Alliance is well positioned to become the central voice to communicate and promote the value of the system design ecosystem as a vital component of the global electronics industry. As this edition of the ESD Alliance newsletter highlights, our membership is growing, our initiatives expanding and we’re offering more events and opportunities. If your company is not a member as yet, please consider joining now. To learn more about the ESD Alliance and how your company can become a member, contact me at bob[at]esd-alliance[dot]org or visit www.esd-alliance.org.



ESD Alliance Welcomes New Members

The ESD Alliance welcomes two new members, Silvaco, Inc. and C-Sky Microsystems.

Silvaco LogoSilvaco, a leading EDA provider of software tools used for process and device development and for analog/mixed-signal, power IC and memory design, joined because it has a growing portfolio of production-proven intellectual property (IP) cores. Additional information is available in the news release.

C-SKY LogoC-Sky Microsystems is first intellectual property (IP) company from China to join the ESD Alliance, C-Sky intends to become an active member of the Semiconductor IP Working Group, helping develop a common methodology and best practices for IP fingerprinting. Other initiatives of interest to C-Sky include the Multi-Die Working Group and the Market Statistics Service (MSS) as well. For additional details, see the news release.



ESD Alliance to Exhibit at Upcoming Events

ARM TechConThe  ESD Alliance will be staffing booths at the upcoming ARM TechCon on October 25th – 27th, in Santa Clara, CA. The Alliance will also be exhibiting at the MEPTEC Heterogeneous Integration Roadmaps Symposium on November 14th in San Jose, CA, and REUSE on December 1st in Mountain View, CA. See the Committee Updates for additional information! Be sure to stop by to say hello.



Committee Updates

Larry Disenhof

Export (Larry Disenhof, Cadence). The export committee continues to monitor government activities and rulings that might have a significant impact on your business.

Of special interest to all exporters is the new Definitions Rules adopted by the Commerce and State Departments as of September 1st. The Agencies clarified what they defined as an export (transfer of goods or technology to a non-US person or destination) and re-export (US goods or technology previously exported being transferred to a follow-on destination.) 

What might be most important on the Commerce side pertains to the use of cloud computing in transferring technology. These new changes the definition of export from the point in time technology leaves the US, to the point in time when the foreign party accesses the decrypted technology. There are guidelines to follow (strength of encryption; the servers cannot be in certain countries, etc.) but with this definition change you will have an increased ability to use cloud services while maintaining compliance. Note that the State Department has *not* fully adopted this rule yet, but they are in deep discussion on moving towards this policy. Additionally, the Definitions Rule clarifies when the regulations apply to university instruction, fundamental research, conference attendance, etc.

The BIS website includes a link to Frequently Asked Questions, which should be useful as you review the Commerce final rule and are available at https://goo.gl/RMfyeU.

In September, the ESD Alliance committee drafted and filed a letter in response to a proposed rule concerning DFARs contract clauses, that if enacted pose serious concerns for the protection of your intellectual property.  The proposed rule can be found at https://goo.gl/OvKPps.

Finally – as you should know by now, the temporary General Export License that allows for exports to two of the Sanctioned ZTE entities was extended to November 28th. We understand that ZTE and the U.S. Government are working actively towards an agreement.

ESD Alliance member companies who need more information regarding these or other government issues potentially affecting your business should contact us.

John Harms

License Management & Anti-Piracy (LMA) (John Harms, Mentor). Monthly LMA meetings continue to include discussions regarding various licensing technologies.  For example, in June the LMA committee participated in the annual meeting with Centralized Enterprise License Users Group (CELUG) members June 7th-8th, co-located with DAC. CELUG includes representatives from most of the enterprise-level users of electronic system design tools, providing an excellent sounding board for various customer licensing issues.  On June 9th, the LMA Committee held closed meetings with representatives from four suppliers of licensing/security software to discuss current and future technologies to address licensing problems.  In August, the group met via teleconference with a fifth vendor; also ESD Alliance-LMA members continue to receive supplemental information from the licensing vendors who presented in June. 

At a special ESD Alliance-LMA teleconference on July 28th, the LMA committee considered and approved a Proof-of-Concept initiative for a method to handle uncontrolled server cloning.  Two small sub-groups were defined: 1) ESD Alliance-LMA engineering reps for the POC from Cadence, Mentor, and Synopsys; 2) Customer reps from CELUG, to answer user perspective questions, review relevant specs, and comment on demos as POC work progresses.  At the recent ESD Alliance Board meeting, the Directors expressed continued support of the group's current plans to deal with this important topic. 

Stephanie ChouInteroperability (Stephanie Chou, Keysight Technologies). The committee continues to evaluate upcoming operating system releases from Red Hat, SUSE, Microsoft and Canonical, as well as the evolution of virtual machine, remote access and cloud computing technologies to address compatibility, long-term support, stability and quality. While tool vendors are free to support other operating systems, a core set, common to most tool vendors, is available on the ESD Alliance web site (esd-alliance.org). The Roadmap is reviewed and updated as needed throughout the year.

The OS Roadmap, available to the electronic design ecosystem, helps vendors and designers focus on a limited number of operating systems. This significantly reduces development and support costs for vendors, while also reducing support and infrastructure costs for design companies.  Operating systems fall into 3 major categories. “Active” is for OSs that are currently supported, with vendor support plans extending long enough to support the long life cycles of complex electronic designs. “Future” suggests the OS has not yet been fully tested by the EDA vendors, but it is expected it will be “active” in the near future. “Deprecated” implies the OS is near the end of its supported lifecycle, thus it is not recommended for starting new designs. This information can help decide what operating systems to use for product design.

Paul CohenIndustry revenue by regionMarket Statistics Service (MSS): (Paul Cohen, ESD Alliance). The ESD Alliance’s MSS report captures EDA, semiconductor IP and services revenue data reported in complete confidence by companies providing these products and services and organizes it into a published report available to members.  The most recent report, covering through Q2, 2016, shows quarterly industry revenue up 5.6% compared to Q2, 2015 on revenues of $2 billion. In addition to the revenue history by product category (above) the MSS report also shows interesting historical geographic trends.

Steve Pollock Emerging Companies (Steve Pollock, AiPac). The Emerging Companies Committee continues to hold informative events on topics of interest to the electronic design ecosystem. We are busy planning a number of events – check the Alliance web site, esd-alliance.org, for details! Recordings of past events are available in the ESD Alliance media library.

On November 1st, we will be holding the next installment of the legal series “Maximizing Your Exit Value” organized by Mark White. Mark is a partner at White Summers Caffee & James, LLP, and general counsel for the ESD Alliance. Visit the Alliance web site for details and registration.

In January, we resume the popular Jim Hogan Emerging Companies Series, when Jim will interview Dave Patterson, with a focus on innovation and Berkeley’s open source RISC processor. 

Graham BellTradeshow (Graham Bell). The committee represents the interests of ESD Alliance companies at the Design Automation Conference (DAC) and the Design Automation and Test Europe (DATE) tradeshow.

DAC logoThe 53rdDAC was a great showcase for ESD Alliance companies and their products. Overall attendance increased compared to the 50th DAC (the first DAC held in Austin), while technical conference attendees increased 45%. The 54th DAC will again be held in Austin, TX, on June 18th through 22nd, 2017.

DATE logoDATE 2017 will be held March 27th-31st, 2017, at the Swiss Tech Convention Center, Lausanne, Switzerland. The 20th DATE conference and exhibition is the main European event bringing together designers and design automation users, researchers and vendors, as well as specialists in the hardware and software design, test and manufacturing of electronic circuits and systems. It puts strong emphasis on ICs and SoCs, reconfigurable hardware and embedded systems, including embedded software.

Warren SavageNEW! IP (Warren Savage, Silvaco) Semiconductor IP is the fastest growing part of the industry and as reported in the Q3 MSS, outpacing EDA for the first time in history.

SIP panel audienceIn September, the Alliance sponsored a panel on challenges faced by Semiconductor IP companies and users, “Semiconductor IP Issues that Keep You Up at Night”. This event, hosted by Silvaco, included an introduction to IP reuse issues followed by a panel discussion featuring industry experts.

SIP panelistsRecognizing the increasing importance of this segment of the industry, the ESD Alliance is a supporter of REUSE, a new trade show and conference focusing on providing a forum for the industry to come together.  REUSE2016The inaugural REUSE event will be held at the Computer History Museum in Mountain View, CA on December 1st, 2016. Attendance is free and open to all companies interested in semiconductor IP, verification IP, and embedded software. Visit the REUSE web site for additional information.

Herb Reiter NEW! System Scaling (Herb Reiter, eda 2 asic). This new initiative brings together IC manufacturers and designers to enable the widespread use of system scaling technologies such as 3D-IC and other multi-die approaches. In a recent blog, working group chair Herb Reiter substantiated the need for bridging the current divide between these two industry groups.

To encourage closer cooperation, the Electronic System Design Alliance will be sponsoring and exhibiting at the MEPTEC Heterogeneous Integration Roadmaps Symposium on November 14th in San Jose, CA. MEPTEC 2016This symposium includes a series of talks by well-known IC industry experts and offers opportunities to meet many exhibitors with capabilities affecting SoC and multi-die IC design, assembly and packaging. Attend this symposium to get an update on IC manufacturing capabilities, and be sure to visit the ESD Alliance booth to hear about our efforts to bridge the great divide.

To help encourage cooperation between manufacturing and design, the Alliance issued the “Multi-Die IC Users Guide”, available as a free download from the Alliance web site, includes inputs from 35 IC design AND manufacturing companies.  Currently, we are soliciting additional inputs for the next revision, planned for release in January, 2017.


 

The ESD Alliance –– Where Electronics Begins
The ESD Alliance newsletter is a quarterly publication of the ESD Alliance.
Volume 3, Number 3


Executive Director Bob Smith 

Board of Directors

Co-Chairmen
Lip-Bu Tan, Cadence Design System
John Kibarian, PDF Solutions 

Directors
Aart de Geus, Synopsys, Inc.
Dean Drako, IC Manage
Amit Gupta, Solido Design
Lucio Lanza, Lanza techVentures
Grant Pierce, Sonics, Inc.
Walden C. Rhines, Mentor Graphics Corporation
Simon Segars, ARM

Editor Paul Cohen

Contributors
Graham Bell, Real Intent
Stephanie Chou, Keysight Technologies
Paul Cohen, ESD Alliance
Nanette Collins, Nanette V. Collins Marketing & PR
Larry Disenhof, Cadence
John Harms, Mentor
Steve Pollock, Semi-Pac
Herb Reiter, eda 2 asic Consulting
Julie Rogers, ESD Alliance
Warren Savage, IPextreme

Electronic System Design Alliance
3081 Zanker Road, San Jose, Calif. 95134
Phone: (408) 287-3322 
Website: esd-alliance.org